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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C630 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". TMP91C630 CMOS 16-Bit Microcontrollers TMP91C630F 1. Outline and Features TMP91C630 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. 2 Kbytes of boot ROM is built-in. The standard name of this microcontroller is TMP91C630F-7770 with ROM code (7770). The package of TMP91C630 is 100-pin flat type. The features are shown below. (1) High-speed 16-bit CPU (900/L1 CPU) Instruction mnemonics are upward-compatible with TLCS-90/900 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: Four-channels (444 ns/2 bytes at 36 MHz) (2) Minimum instruction execution time: 111 ns (at 36 MHz) (3) Built-in RAM: 6 Kbytes Built-in ROM: None Built-in Boot ROM: 2 Kbytes (4) External memory expansion Expandable up to 16 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus Dynamic data bus sizing (5) 8-bit timers: 6 channels (6) 16-bit timer/event counter: 1 channel (7) Serial bus interface: 2 channels (8) 10-bit AD converter: 8 channels (9) Watchdog timer 030619EBP1 The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 91C630-1 2003-07-22 TMP91C630 (10) Chip Select/Wait controller: 4 blocks (11) Interrupts: 35 interrupts 9 CPU interrupts: Software interrupt instruction and illegal instruction 19 internal interrupts: 7 priority levels are selectable. 7 external interrupts: 7 priority levels are selectable. (Level mode, rising edge mode and falling edge mode are selectable.) (12) Input/output ports: 53 pins (13) Standby function Three halt modes: Idle2 (programmable), Idle1, Stop (14) Operating voltage VCC (15) Package 100-pin QFP: P-LQFP100-1414-0.50F 2.7 V to 3.6 V (fc max 36 MHz) 91C630-2 2003-07-22 TMP91C630 ADTRG (AN3/PA3) AN0~AN7 (PA0~PA7) VREFH VREFL AVCC AVSS CPU (TLCS-900L1) DVCC [4] DVSS [4] BOOT 10-bit 8-ch AD converter Port A XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits AM0/AM1 RESET OSC Clock gear Port 1 Port 2 X1 X2 EMU0 EMU1 (P10~P17) D8~D15 (P20~P27) A16~A23 SR F PC RD WR PZ2 ( HWR ) PZ3 Port Z Watchdog timer (WDT) Data bus Address bus Serial I/O (channel 0) Port 5 Serial I/O (channel 1) D0~D7 A0~A7 A8~A15 TXD0 (P80) RXD0 (P81) SCLK0/ CTS0 (P82) STS0 (P83) TXD1 (P84) RXD1 (P85) SCK1/ CTS1 (P86) STS1 (P87) BUSRQ (P53) BUSAK (P54) Port 8 WAIT (P55) TA0IN/INT1 (P70) TA1OUT (P71) 8-bit timer (TMRA0) 8-bit timer (TMRA1) 6-KB RAM 8-bit timer (TMRA2) CS/WAIT controller (4 blocks) CS0 (P60) CS1 (P61) CS2 (P62) CS3 (P63) Interrupt controller NMI INT0 (P56) TA3OUT/INT2 (P72) 8-bit timer (TMRA3) TB0IN0 (P93) TB0IN1 (P94) TB0OUT0 (P95) TB0OUT1 (P96) INT5 (P90) TA4IN/INT3 (P73) TA5OUT (P74) INT4 (P75) 8-bit timer (TMRA4) 8-bit timer (TMRA5) Port 7 2-KB boot ROM 16-bit timer (TMRB0) Port 9 Figure 1.1 TMP91C630 Block Diagram 91C630-3 2003-07-22 TMP91C630 2. 2.1 Pin Assignment and Pin Functions The Pin Assignment and Pin Functions of the TMP91C630F are showed in Figure 2.1.1. Pin Assignment Diagram Figure 2.1.1 shows the pin assignment of the TMP91C630F. Pin Pin Name DVCC BOOT Pin Name P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 A15 A14 A13 A12 Pin No. No. 64 65 66 67 68 69 70 71 72 73 74 75 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 TMP91C630F 40 86 39 87 38 88 37 89 Top view 36 90 35 91 34 92 P-LQFP100-1414-0.50F 33 93 32 94 31 95 30 96 29 97 28 98 27 99 26 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 63 62 61 60 59 58 57 56 55 54 53 52 51 DVSS P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 D7 D6 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RD WR DVCC PZ2/ HWR DVSS PA0/AN0 PA1/AN1 PA2/AN2 PA3/AN3/ ADTRG PA4/AN4 PA5/AN5 PA6/AN6 PA7/AN7 100 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 D5 D4 D3 D2 D1 D0 P96/TB0OUT1 P95/TB0OUT0 P94/TB0IN1 P93/TB0IN0 P90/INT5 P75/INT4 P74/TA5OUT P73/TA4IN/INT3 P72/TA3OUT/INT2 P71/TA1OUT P70/TA0IN/INT1 RESET AM1 X1 DVSS X2 DVCC AM0 P63/ CS3 VREFH VREFL AVSS AVCC NMI DVSS P53/ BUSRQ DVCC P54/ BUSAK P55/ WAIT P56/INT0 PZ3 P80/TXD0 1 2 3 4 5 6 7 8 9 10 11 12 13 25 24 23 22 21 20 19 18 17 16 15 14 P62/ CS2 P61/ CS1 P60/ CS0 EMU1 EMU0 P87/ STS1 P86/SCLK1/ CTS1 P85/RXD1 P84/TXD1 P83/ STS0 P82/SCLK0/ CTS0 P81/RXD0 Figure 2.1.1 Pin Assignment Diagram (100-Pin LQFP) 91C630-4 2003-07-22 TMP91C630 2.2 Pin Names and Functions The names of the Input/Output pins and their functions are described below. Table 2.2.1 to Table 2.2.3 show Pin name and functions. Table 2.2.1 Pin Names and Functions (1/3) Pin Names D0 to D7 P10 to P17 D8 to D15 P20 to P27 A16 to A23 A8 to A15 A0 to A7 RD WR Number of Pins 8 8 I/O I/O I/O I/O Functions Data (lower): Bits 0 to 7 of data bus Port 1: I/O port that allows I/O to be selected at the bit level (When used to the external 8-bit bus) Data (upper): Bits 8 to15 of data bus Port 2: Output port Address: Bits 16 to 23 of address bus Address: Bits 8 to 15 of address bus Address: Bits 0 to 7 of address bus Read: Strobe signal for reading external memory Write: Strobe signal for writing data to pins D0 to D7 Port 53: I/O port (with pull-up resistor) Bus request: Signal used to request bus release (high-impedance). Port 54: I/O port (with pull-up resistor) Bus acknowledge: Signal used to acknowledge bus release (high-impedance). Port 55: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait. ((1 N) waits mode) 8 8 8 1 1 1 1 Output Output Output Output Output Output I/O Input I/O Output I/O Input I/O Input Output Output Output Output Output Output Output Output I/O Input Input I/O Output I/O Output Input P53 BUSRQ P54 BUSAK P55 WAIT 1 1 P56 INT0 P60 CS0 Port 56: I/O port (with pull-up resistor) Interrupt request pin0: Interrupt request pin with programmable level/rising edge/falling edge Port 60: Output port Chip select 0: Outputs 0 when address is within specified address area. Port 61: Output port Chip select 1: Outputs 0 when address is within specified address area. Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area. Port 63: Output port Chip select 3: Outputs 0 when address is within specified address area. Port 70: I/O port 8-bit TMRA0 input Interrupt request pin 1: Interrupt request pin with programmable level/rising edge/falling edge Port 71: I/O port 8-bit TMRA0 or 8-bit TMRA1 output Port 72: I/O port 8-bit TMRA2 or 8-bit TMRA3 output Interrupt request pin 2: Interrupt request pin with programmable level/rising edge/falling edge 1 1 1 1 1 P61 CS1 P62 CS2 P63 CS3 P70 TA0IN INT1 P71 TA1OUT P72 TA3OUT INT2 1 1 91C630-5 2003-07-22 TMP91C630 Table 2.2.2 Pin Names and Functions (2/3) Pin Names P73 TA4IN INT3 P74 TA5OUT P75 INT4 P80 TXD0 P81 RXD0 P82 SCLK0 CTS0 Number of Pins 1 I/O I/O Input Input I/O Output I/O Input I/O Output I/O Input I/O Input I/O I/O I/O Output I/O Input I/O Input I/O I/O I/O Input I/O Input I/O Input I/O Output I/O Output Input Input Input I/O Output I/O Functions Port 73: I/O port 8-bit TMRA4 input Interrupt request pin 3: Interrupt request pin with programmable level/rising edge/falling edge. Port 74: I/O port 8-bit TMRA4 or 8-bit TMRA5 output Port 75: I/O port Interrupt request pin 4: Interrupt request pin with programmable Port 80: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin Port 81: I/O port (with pull-up resistor) Serial receive data 0 Port 82: I/O port (with pull-up resistor) Serial clock I/O 0 Serial data send enable 0 (Clear to send) Port 83: I/O port (with pull-up resistor) Serial data request signal 0 Port 84: I/O port (with pull-up resistor) Serial send data 0: Programmable open-drain output pin Port 85: I/O port (with pull-up resistor) Serial receive data 1 Port 86: I/O port (with pull-up resistor) Serial clock I/O 1 Serial data send enable 1 (Clear to send) Port 87: I/O port (with pull-up resistor) Serial data request signal 1 Port 90: I/O port Interrupt request pin 5: Interrupt request pin with programmable level/rising edge/falling edge Port 93: I/O port Timer B0 input 0 Port 94: I/O port Timer B0 input 1 Port 95: I/O port Timer B0 output 0 Port 96: I/O port Timer B0 output 1 Port A0 to A7: Pins used to input port. Analog input 0 to 7: Pins used to input to AD converter. AD trigger: Signal used to request AD start (PA3). Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) 1 1 1 1 1 P83 STS0 1 1 1 1 P84 TXD1 P85 RXD1 P86 SCLK1 CTS1 P87 STS1 1 1 P90 INT5 P93 TB0IN0 P94 TB0IN1 P95 TB0OUT0 P96 TB0OUT1 PA0 to PA7 AN0 to AN7 ADTRG 1 1 1 1 8 PZ2 HWR 1 1 PZ3 91C630-6 2003-07-22 TMP91C630 Table 2.2.3 Pin Names and Functions (3/3) Pin Names BOOT Number of Pins 1 1 2 I/O Input Input Input Functions This pin sets boot mode (with pull-up resistor) Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Operation mode: AM1 0 and AM0 AM1 0 and AM0 1: External 16-bit bus is fixed or external 8-/16-bit buses are mixed. 0: External 8-bit bus is fixed. NMI AM0 to AM1 RESET 1 1 1 1 1 2 4 4 1 1 Input Input Input I/O Reset: Initializes TMP91C630 (with pull-up resistor) Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND supply pin for AD converter Oscillator connection pins Power supply pins GND pins (0 V) VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS EMU0 EMU1 Output Output Open pin Open pin Note 1: An external DMA controller cannot access the device's built-in memory or built-in I/O devices using the BUSRQ and BUSAK signals. 91C630-7 2003-07-22 TMP91C630 3. Operation This section describes the basic components, functions and operation of the TMP91C630. Notes and restrictions which apply to the various items described here are outlined in section 7. Precautions and restrictions at the end of this databook. 3.1 CPU The TMP91C630 incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For a description of this CPU's operation, please refer to the section of this databook which describes the TLCS-900/L1 CPU. The following sub-sections describe functions peculiar to the CPU used in the TMP91C630; these functions are not covered in the section devoted to the TLCS-900/L1 CPU. 3.1.1 Reset When resetting the TMP91C630 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to Low level at least for 10 system clocks (ten states: 8.89 s at 36 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by Reset operation. It means that the system clock mode fSYS is set to fc/32 ( fc/16 1/2). When the reset has been accepted, the CPU performs the following: Sets the program counter (PC) as follows in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<0:7> PC<8:15> PC<16:23> Data in location FFFF00H Data in location FFFF01H Data in location FFFF02H Sets the stack pointer (XSP) to 100H. Sets bits 91C630-8 2003-07-22 fFPH Sampling Sampling RESET A23 to A0 0FFFF00H CS0, CS1, CS3 CS2 Figure 3.1.1 shows the timing of a reset for the TMP91C630. Figure 3.1.1 TMP91C630 Reset Timing Example Data-in Data-out 91C630-9 (PZ2 input mode) D0 to D15 Data-in Read RD (After reset released, startting 2 waits read cycle) D0 to D15 Write WR HWR TMP91C630 2003-07-22 Note: Pull-up (Internal) High-Z TMP91C630 3.2 Outline of Operation Modes There are multi-chip and multi-boot modes. Which mode is selected depends on the device's pin state after a reset. Multi-chip mode: The device normally operations in this mode. After a reset, the device starts executing the external memory program. Multi-boot mode: This mode is used to rewrite the external flash memory by serial transfer (UART). After a reset, internal boot program starts up, executing a on-board rewrite program. Table 3.2.1 Operation Mode Setup Table Operation Mode Multi-chip mode Multi-boot mode Mode Setup Input Pin RESET BOOT H L 91C630-10 2003-07-22 TMP91C630 3.3 Memory Map Figure 3.3.1 is a memory map of the TMP91C630. Multi-chip mode 000000H 000100H Internal I/O (4 Kbytes) 000000H 000100H Multi-boot mode Internal I/O (4 Kbytes) Direct area (n) 001000H Internal RAM (6 Kbytes) 002800H External memory 01F800H Internal boot ROM (2 Kbytes) 01FFFFH 001000H Internal RAM (6 Kbytes) 002800H External memory 16-Mbyte area (r32) ( r32) (r32 ) (r32 d8/16) (r32 r8/16) (nnn) External memory FFFF00H FFFFFFH Vector table (256 bytes) FFF800H FFFEFFH FFFF00H FFFFFFH Internal boot ROM (2 Kbytes) Vector table (256 bytes) ( Internal area) Figure 3.3.1 TMP91C630 Memory Map 91C630-11 2003-07-22 TMP91C630 3.4 Triple Clock Function and Standby Function The TMP91C630 system clock block contains (1) Clock gearing system (2) Standby controller (3) Noise reducing circuit It can be used for low-power, low-noise systems. The system clock operating mode (single clock mode) is shown in Figure 3.4.1. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode ( only oscillator operate) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Clock mode transition figure Figure 3.4.1 System Clock Block Diagram The clock frequency input from the X1 and X2 pins is called fc. In case of TMP91C630, fc fFPH. The system clock fSYS is defined as the divided clock of fFPH, and one cycle of fSYS is regarded to as one state. 91C630-12 2003-07-22 TMP91C630 3.4.1 Block Diagram of System Clock SYSCR2 SYSCR0 Warming up timer (High-frequency oscillator) T T0 fc/16 fFPH 2 4 fFPH fc fc/2 fc/4 fc/8 fc/16 2 fSYS X1 X2 High-frequency oscillator 2 4 8 16 fOSCH SYSCR1 Clock gear fSYS TMRA01 to TMRA45 T0 Prescaler CPU ROM RAM TMRB0 Prescaler Interrupt controller WDT I/O ports SIO0, SIO1 Prescaler Figure 3.4.2 Block Diagram of System Clock 91C630-13 2003-07-22 TMP91C630 SFRs 7 SYSCR0 (00E0H) Bit symbol Read/Write After reset Function 1 Always write 1 0 Always write 0 1 Always write 1 0 Always write 0 R/W 0 Always write 0 0 Always write 0 0 00: fFPH 01: Reserved 10: fc/16 11: Reserved 0 Select prescaler clock 6 5 4 3 2 1 PRCK1 0 PRCK0 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 2 GEAR2 R/W 1 GEAR1 0 0 GEAR0 0 0 Always write 0 1 Select gear value of high frequency (fc) 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function 6 R/W 0 Always write 0 5 WUPTM1 R/W 1 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 0 DRVE R/W 0 1: Drive the pin during STOP mode Warm-up timer 00: Reserved 01: 28/Input frequency 10: 214 11: 216 Figure 3.4.3 SFR for System Clock 91C630-14 2003-07-22 TMP91C630 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON 6 R/W 0 Always write 0 5 R/W 1 Always write 1 4 R/W 0 Always write 0 3 R/W 0 Always write 0 2 EXTIN R/W 0 1: External clock 1 R/W 1 Always write 1 0 R/W 1 Always write 1 EMCCR1 (00E4H) Bit symbol Read/Write After reset Function Writing 1FH turns protections off. Writing any value except 1FH turns protection on. Figure 3.4.4 SFR for Noise-Reducing 91C630-15 2003-07-22 TMP91C630 3.4.2 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 For example, fSYS is set to 1.125 MHz when the 36 MHz oscillator is connected to the X1 and X2 pins. Clock gear controller The fFPH is set according to the contents of the clock gear select register SYSCR1 SYSCR1 EQU LD X: Don't care 00E1H (SYSCR1), XXXX0000B ; Changes fSYS to fc/2. (Changing to high-frequency clock gear) To change the clock gear, write the appropriate value to the SYSCR1 SYSCR1 EQU 00E1H LD (SYSCR1), XXXX0001B ; Changes fSYS to fc/4. LD (DUMMY), 00H ; Dummy instruction Instruction to be executed after clock gear has changed. 91C630-16 2003-07-22 TMP91C630 3.4.3 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA45, TMRB0 and SIO0, SIO1) there is a prescaler which can divide the clock. The T clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 2. The setting of the SYSCR0 3.4.4 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Single drive for high-frequency oscillator (2) Protection of register contents The above functions are performed by making the appropriate settings in the EMCCR0 and EMCCR1 registers. (1) Single drive for high-frequency oscillator (Purpose) Not need twin-drive and protect mistake-operation by inputted noise to X2 pin when the external-oscillator is used. (Block diagram) fOSCH X1 pin Enable oscillation (STOP EMCCR0 X2 pin (Setting method) When a 1 is written to the EMCCR0 91C630-17 2003-07-22 TMP91C630 (2) Runaway provision with protection register (Purpose) Provision against runaway of program caused by noise mixing etc. If specified SFR (clock and memory control register) is changed in runaway state, memory access is impossibility. By setting protection register, write operation to specified SFR (clock register and memory control register) can be prohibited. Specified SFR list 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear (write enable only EMCCR1) SYSCR0, SYSCR1, SYSCR2, EMCCR0 (Block diagram) Protect register EMCCR0 Write signal to SFR (Setting method) If writing except "1FH" code to EMCCR1 register, it become protect ON. By this operation, write operation to specified SFR is disabling. If writing "1FH" code to EMCCR1 register, it become protect OFF. State of protect can be confirmed by reading EMCCR0 91C630-18 2003-07-22 TMP91C630 3.4.5 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 Table 3.4.1 The Registers of Setting Operation during IDLE2 Mode Internal I/O TMRA01 TMRA23 TMRA45 TMRB0 SIO0 SIO1 AD converter WDT SFR TA01RUN b. c. IDLE1: Only the oscillator to operate. STOP: All internal circuits stop operating. The operation of each different HALT mode is described in Table 3.4.2. Table 3.4.2 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA, TMRB Block SIO AD converter WDT Interrupt controller Operational Can be selected Stopped IDLE2 11 Stop IDLE1 10 STOP 01 See Table 3.4.5 Maintain same state as when HALT instruction was executed. 91C630-19 2003-07-22 TMP91C630 (2) How to clear a HALT mode The Halt state can be cleared by a reset or by an interrupt request. The combination of the value in 91C630-20 2003-07-22 TMP91C630 Table 3.4.3 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of halt state clearance NMI Interrupt Enabled Interrupt Disabled (Interrupt Level) (Interrupt Mask) (Interrupt Level) < (Interrupt Mask) IDLE2 IDLE1 STOP *1 IDLE2 IDLE1 STOP INTWDT INT0 to INT4 (Note) *1 *1 Interrupt INT5 INTTA0 to INTTA5 INTTB00, INTTB01, INTTBOF0 INTRX0, INTTX0 INTRX1, INTTX1 INTAD RESET Reset initializes the LSI : After clearing the HALT mode, CPU starts interrupt processing. : After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. : Cannot be used to clear the HALT mode. : The priority level (interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1: The HALT mode is cleared when the warm-up time has elapsed. Note: When the HALT mode is cleared by INT0 to INT4 interrupt of the level mode in the interrupt enabled status, hold the level until starting interrupt processing. Changing level before holding level, interrupt processing is correctly started. Example: Clearing IDLE1 mode An INT0 interrupt clears the Halt state when the device is in IDLE1 mode. Address 8203H 8206H 8209H 820BH 820EH INT0 LD LD EI LD HALT (IIMC0), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91C630-21 2003-07-22 TMP91C630 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.4.5 illustrates an example of the timing for clearance of the IDLE2 mode Halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Clearing interrupt IDLE2 mode Figure 3.4.5 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator continue to operate. The system clock in the MCU stops. In the Halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (i.e. restart of operation) is synchronous with it. Figure 3.4.6 illustrates the timing for clearance of the IDLE1 mode Halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Clearing interrupt IDLE1 mode Figure 3.4.6 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C630-22 2003-07-22 TMP91C630 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. pin status in STOP mode depends on the settings in the SYSCR2 Figure 3.4.7 illustrates the timing for clearance of the STOP mode Halt state by an interrupt. Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data interrupt for release STOP mode Figure 3.4.7 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.4.4 Sample Warm-up Times After Clearance of STOP Mode at fOSCH 36 MHz SYSCR2 7.1 s 8 10 (2 ) 0.455 ms 14 11 (2 ) 1.820 ms 16 91C630-23 2003-07-22 TMP91C630 Table 3.4.5 Pin States in STOP Mode Pin Names D0 to D7 P10 to P17 (D8 to D15) I/O Input/output mode Input mode Output mode Input/output mode Output pin Output pin Input mode Output mode Input mode Output mode Output mode Input mode Output mode Input mode Output mode Input mode Output mode Input mode Input pin Input Input Input Output 0 1 Output Output Output Input Output Input Output Output Input Output Input Output Input Output Input Input Input High level output Input Input Input High level output P20 to P27 (A16 to A23), A0 to A15 RD , WR PZ2, PZ3 P53 to P56 P60 to P63 P70 to P75 P80 to P87 P90, P93 to P96 PA0 to PA7 NMI RESET AM0, AM1 X1 X2 : As for input mode/input pin, input gate is closed. Output mode/output pin is at high impedance. Input: Input gate is in operation. Fix input voltage to L or H. Output: Output state 91C630-24 2003-07-22 TMP91C630 3.5 Interrupts Interrupts are controlled by the CPU interrupt mask register SR 91C630-25 2003-07-22 TMP91C630 Interrupt processing Interrupt appointed by micro DMA start vector? No Yes Clear interrupt request flag Interrupt vector calue "V" read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA Count PUSH PUSH SR Count 1 Micro DMA processing Count 0 No Yes INTNEST Clear vector register generating micro DMA transfer end interrupt (INTTC0 to INTTC3) PC (FFFF00H V) Interrupt processing program RETI instruction POP POP INTNEST SR PC INTNEST 1 End Figure 3.5.1 Interrupt and Micro DMA Processing Sequence 91C630-26 2003-07-22 TMP91C630 3.5.1 General-Purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: the smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1( 1) to the interrupt mask register 91C630-27 2003-07-22 TMP91C630 Table 3.5.1 TMP91C630 Interrupt Vectors and Micro DMA Start Vectors Default Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 to Maskable Non-mask able Type Interrupt Source or Source of Micro DMA Vector Value Request Reset or [SWI0] instruction [SWI1] instruction Illegal instruction or [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction NMI : NMI pin input Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48F FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H to FFFFFCH Micro DMA Start Vector 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H to 00FCH INTWD: Watchdog timer Micro DMA INT0: INT0 pin input INT1: INT1 pin input INT2: INT2 pin input INT3: INT3 pin input INT4: INT4 pin input INT5: INT5 pin input (Reserved) (Reserved) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 (Reserved) (Reserved) INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) (Reserved) (Reserved) INTTBOF0: 16-bit timer 0 (Overflow) (Reserved) INTRX0: Serial receive (Channel 0) INTTX0: Serial transmission (Channel 0) INTRX1: Serial receive (Channel 1) INTTX1: Serial transmission (Channel 1) (Reserved) (Reserved) INTAD: AD conversion end INTTC0: Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) (Reserved) 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH to 91C630-28 2003-07-22 TMP91C630 3.5.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C630 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. Micro. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a stand-by mode by HALT instruction, the requirement of micro DMA will be ignored (pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on 91C630-29 2003-07-22 TMP91C630 This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see (4) Transfer Mode Register. As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 23 interrupts shown in the micro DMA start vectors of Figure 3.5.1 and by the micro DMA soft start, making a total of 24 interrupts. Figure 3.5.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for Counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, trandfer source/transfer destination addresses both even-numberd values). 1 state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Trasfer source address Trasger destination address D0 to D15 Input Output Figure 3.5.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (the address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91C630-30 2003-07-22 TMP91C630 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C815 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing 1 to each bit of DMAR register causes micro DMA once. At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to 0. Only one-channel can be set once for micro DMA. (Do not write 1 to plural bits.) When writing again 1 to the DMAR register, check whether the bit is 0 before writing 1. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is 0 after start up of the micro DMA. Symbol Name DMA software request register Address 89H (no RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 1 DMAR1 0 0 DMAR0 0 DMA request R/W DMAR (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers. Data setting for these registers is done by an "LDC cr, r" instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0: only use LSB 24 bits DMA destination address register 0: only use LSB 24 bits DMA counter register 0: 1 to 65536 DMA mode register 0 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3 DMA destination address register 3 DMA counter register 3 DMA mode register 3 91C630-31 2003-07-22 TMP91C630 (4) Detailed description of the transfer mode register 8 bits DMAM0 to DMAM3 0 0 0 Mode Note: When setting a value in this register, clear 0 to the upper 3 bits. Minimum Number of Execution Time Execution States at fc 36 MHz 8 states 444 ns Number of Transfer Bytes 000 (fixed) 000 00 Byte transfer Mode Description Transfer destination address INC mode ..............I/O to memory (DMADn ) (DMASn) DMACn DMACn 1 If DMACn 0, then INTTCn is generated. Transfer destination address DEC mode ..............I/O to memory (DMADn ) (DMASn) DMACn DMACn 1 If DMACn 0, then INTTCn is generated. Transfer source address INC mode ..............Memory to I/O (DMADn) (DMASn ) DMACn DMACn 1 If DMACn 0, then INTTCn is generated. Transfer source address DEC mode ..............Memory to I/O (DMADn) (DMASn ) DMACn DMACn 1 If DMACn 0, then INTTCn is generated. Fixed address mode ..............I/O to I/O (DMADn) (DMASn ) DMACn DMACn 1 If DMACn 0, then INTTCn is generated. 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer 12 states 667 ns 8 states 444 ns 12 states 667 ns 8 states 444ns 12 states 667 ns 8 states 444ns 12 states 667 ns 8 states 444 ns 12 states 667 ns Counter mode ........ For counting number of times interrupt is generated DMASn DMASn 1 DMACn DMACn 1 If DMACn 0, then INTTCn is generated. 5 states 278 ns Note 1: "n" is the corresponding micro DMA channels 0 to 3 DMADn /DMASn : Post-increment (increment register value after transfer) DMADn /DMASn : Post-decrement (decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (both translation and destination address area)/0 waits/ fc 36 MHz/selected high frequency mode (fc 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91C630-32 2003-07-22 TMP91C630 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 26 interrupt channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to zero in the following cases: when reset occurs when the CPU reads the channel vector after accepted its interrupt when executing an instruction that clears the interrupt (write DMA start vector to INTCLR register) when the CPU receives a micro DMA request (when micro DMA is set) when the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g. INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and Watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (the interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value 91C630-33 2003-07-22 Interrupt controller Interrupt request F/F S R V V Priority encoder IFF2:0 1 7 3 INTRQ2 to 0 6 3 D0 D1 6 Interrupt request signal to CPU 20H 24H Interrupt mask F/F RESET EI 1 to 7 DI Interrupt level detect IFF Q 1 RESET interrupt vector read Priority setting register Dn Dn 1 2 Interrupt request F/F Dn Interrupt request flag 26 V 28H V 2CH V 30H V 34H V 38H V 3CH V 4CH Interrupt vector generator Interrupt vector read D2 D3 D4 D5 D6 D7 Reset Interrupt vector read Micro DMA acknowledge SQ R D Q CLR 3 3 Dn A B C CPU NMI INTWD Decoder Y1 Y2 Y3 Y4 Y5 Y6 1 2 Highest A B 3 priority interrupt C 4 level select 5 6 7 if INTRQ2 to 0 2 to 0 then 1. Interrupt request signal INT0 INT1 INT2 INT3 INT4 INT5 INTTA0 During IDLE1 During STOP Figure 3.5.3 Block Diagram of Interrupt Controller 91C630-34 V 9CH V A0H V A4H V A8H V ACH Micro DMA start vector setting register HALT release RESET INT0, 1, 2, 3, 4 NMI 4-input OR Soft start 34 S 6 Selector A DMA0V DMA1V DMA2V DMA3V B Micro DMA channel priority decoder 2 DQ CLR INTTC 4 if IFF 7 then 0 Micro DMA request Micro DMA counter zero interrupt D5 D4 D3 D2 D1 D0 RESET INTAD INTTC0 INTTC1 INTTC2 INTTC3 0 1 2 3 2 Micro DMA channel specification TMP91C630 2003-07-22 TMP91C630 (1) Interrupt priority setting registers Name Symbol Address INTE0 & INTE0AD INTAD enable INT1 & INT2 enable INT3 & INT4 enable 7 IADC R 0 I2C R 0 I4C R 0 6 INTAD IADM2 0 INT2 I2M2 0 INT4 I4M2 0 5 IADM1 R/W 0 I2M1 R/W 0 I4M1 R/W 0 4 IADM0 0 I2M0 0 I4M0 0 3 I0C R 0 I1C R 0 I3C R 0 I5C R 0 2 INT0 I0M2 0 INT1 I1M2 0 INT3 I3M2 0 INT5 I5M2 0 ITA0M2 0 ITA2M2 0 ITA4M2 1 I0M1 R/W 0 I1M1 R/W 0 I3M1 R/W 0 I5M1 R/W 0 ITA0M1 R/W 0 ITA2M1 R/W 0 ITA4M1 R/W 0 I0M0 0 I1M0 0 I3M0 0 I5M0 0 ITA0M0 0 ITA2M0 0 ITA4M0 Interrupt source Bit symbol Read/Write After reset 90H INTE12 91H INTE34 92H INT5 enable INTE5 93H INTTA0 & INTETA01 INTTA1 enable INTTA2 & INTETA23 INTTA3 enable INTTA4 & INTETA45 INTTA5 enable INTTA1 (TMRA1) 95H ITA1C R 0 ITA3C R 0 ITA5C R 0 0 0 ITA5M2 0 ITA3M2 ITA1M2 ITA1M1 R/W 0 ITA3M1 R/W 0 ITA5M1 R/W 0 0 0 ITA5M0 INTTA5 (TMRA5) 97H ITA4C R 0 0 ITA3M0 INTTA3 (TMRA3) 96H ITA2C R 0 ITA1M0 ITA0C R 0 INTTA0 (TMRA0) INTTA2 (TMRA2) INTTA4 (TMRA4) 0 0 0 lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 91C630-35 2003-07-22 TMP91C630 Name Symbol Address Interrupt enable INTETB0 TMRB0 Interrupt enable INTETBOV TMRB0V (over flow) Interrupt enable serial 0 7 ITB01C R 0 6 5 4 ITB01M0 0 3 ITB00C R 0 ITF0C R 0 2 ITB00M2 0 ITF0M2 0 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 1 0 Interrupt source Bit symbol Read/Write INTTB01 (TMRB0) 99H ITB01M2 ITB01M1 R/W 0 0 (Reserved) 9BH INTTB00 (TMRB0) ITB00M1 ITB00M0 R/W 0 ITF0M1 R/W 0 IRX0M1 R/W 0 IRX1M1 R/W 0 ITC0M1 R/W 0 ITC2M1 R/W 0 0 0 ITC2M0 0 ITC0M0 0 IRX1M0 0 IRX0M0 0 ITF0M0 INTTBOF0 (Overflow) After reset INTTX0 INTES0 9CH ITX0C R 0 0 INTTX1 INTES1 9DH ITX1C R 0 0 INTTC1 A0H ITC1C R 0 ITC3C R 0 0 0 INTTC3 A1H ITC3M2 ITC3M1 R/W 0 0 ITC3M0 ITC2C R 0 ITC1M2 ITC1M1 R/W 0 0 ITC1M0 ITC0C R 0 ITX1M2 ITX1M1 R/W 0 0 ITX1M0 IRX1C R 0 ITX0M2 ITX0M1 R/W 0 0 ITX0M0 IRX0C R 0 Interrupt enable serial 1 INTTC0 & INTETC01 INTTC1 enable INTTC2 & INTETC23 INTTC3 enable lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Interrupt request flag 91C630-36 2003-07-22 TMP91C630 (2) External interrupt control Name Symbol Address 7 6 I2EDGE Interrupt input mode control 0 0 0 5 I2LE 0 4 I1DGE W 0 3 I1LE 0 2 I0EDGE 0 1 I0LE 0 0 NMIREE 0 1: Operate even on rising/falling edge of NMI IIMC0 8CH (no RMW) Write 0 INT2EDGE INT2 0: Edge 0: Rising 1: Level 1: Falling INT1EDGE INT1 0: Edge 0: Rising 1: Level 1: Falling INT0EDGE INT0 0: Edge 0: Rising 1: Level 1: Falling INT2 level enable 0 1 0 1 0 1 0 1 Edge detect INT Level INT Edge detect INT Level INT Edge detect INT Level INT INT request generation at falling edge INT request generation at rising/falling edge INT1 level enable INT0 level enable NMI rising edge enable Name Interrupt input mode control1 Symbol Address 7 6 I5EDGE 5 I5LE 0 4 I4EDGE W 0 3 I4LE 0 2 I3EDGE 0 1 I3LE 0 0 IIMC1 8DH (no RMW) 0 INT5EDGE INT5 0: Edge 0: Rising 1: Level 1: Falling INT4EDGE INT4 0: Edge 0: Rising 1: Level 1: Falling INT3EDGE INT3 0: Edge 0: Rising 1: Level 1: Falling INT5 level enable 0 1 0 1 0 1 Edge detect INT Level INT Edge detect INT Level INT Edge detect INT Level INT INT4 level enable INT3 level enable When switching IIMC0 and 1 registers, first every FC registers in port which built-in INT function clear to 0. 91C630-37 2003-07-22 TMP91C630 Setting functions on external interrupt pins Interrupt Pin NMI Mode Falling edge Both falling and Rising edges Rising edge Falling edge High level Low level Rising edge Falling edge High level Low level Rising edge Falling edge High level Low level Rising edge Falling edge High level Low level Rising edge Falling edge High level Low level Rising edge Falling edge High level Low level Setting Method 0, INT0 INT1 INT2 INT3 INT4 INT5 (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.5.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR Name Symbol Address Interrupt 88H clear INTCLR (no RMW) control 0AH 6 Clears interrupt request flag INT0. 5 CLRV5 7 4 CLRV4 W 0 3 CLRV3 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 0 0 0 Interrupt vector 91C630-38 2003-07-22 TMP91C630 (4) Micro DMA start vector registers These registers assign micro DMA processing to an sets which source corresponds to DMA. The interrupt source whose micro DMA start vector value matches the vector set in one of these registers is designated as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, in order for micro DMA processing to continue, the micro DMA start vector register must be set again during processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the lowest numbered channel takes priority. Accordingly, if the same vector is set in the micro DMA start vector registers for two different channels, the interrupt generated on the lower-numbered channel is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel has not been set in the channel's micro DMA start vector register again, micro DMA transfer for the higher-numbered channel will be commenced. (This process is known as micro DMA chaining.) Name Symbol Address DMA0 start vector 80H (no RMW) 7 6 5 DMA0V5 0 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 DMA0 start vector DMA0V R/W DMA1 start vector DMA1 start vector DMA1V 81H (no RMW) DMA1V5 0 DMA2 start vector DMA2V5 0 DMA3 start vector DMA3V5 R/W DMA2 start vector DMA2V 82H (no RMW) R/W DMA3 start vector DMA3V 83H (no RMW) R/W 0 0 0 0 0 0 (5) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches zero. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to 1 specifies that any micro DMA transfer on that channel will be a burst transfer. Name Symbol Address DMA software request register DMA burst register 89H (no RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 2 DMAR2 R/W 0 DMAB2 R/W 0 1 DMAR1 R/W 0 DMAB1 0 0 DMAR0 R/W 0 DMAB0 0 DMAR 1: DMA software request DMAB 8AH (no RMW) 0 91C630-39 2003-07-22 TMP91C630 (6) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore if, immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag (Note), the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector. In this case, the CPU will read the default vector 0008H and jump to interrupt vector address FFFF08H. To avoid this, an instruction which clears an interrupt request flag should always be preceded by a DI instruction. Thus, before a POP SR instruction is executed, changing the value of the interrupt mask register INT0 to 5 level mode In Level mode INT0 is not an edge-triggered interrupt. Hence, in Level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from Edge mode to Level mode, the interrupt request flag is cleared automatically. (For example: in case of INT0) If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to Level mode so as to release a HALT state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the HALT state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the HALT state has been released.) When the mode changes from Level mode to Edge mode, interrupt request flags which were set in Level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC0), 00H; Switches interrupt input mode from Level mode to Edge mode. LD (INTCLR), 0AH; Clears interrupt request flag. EI INTRX The interrupt request flip-flop can only be cleared by a Reset or by reading the Serial channel receive buffer. It cannot be cleared by an instruction. Note: The following instructions or pin input state changes are equivalent to instructions which clear the interrupt request flag. INT0 to 5: Instructions which switch to Level mode after an interrupt request has been generated in Edge mode. The pin input changes from High to Low after an interrupt request has been generated in Level mode (H L). INTRX: Instructions which read the Receive buffer 91C630-40 2003-07-22 TMP91C630 3.6 Port Functions The TMP91C630 features 53-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.6.1 lists the functions of each port pin. Table 3.6.2 lists I/O registers and their specifications. Table 3.6.1 Port Functions (R: with programmable pull-up resistor) Pin Name for Internal Function D8 to D15 A16 to A23 BUSRQ BUSAK Port Name Port 1 Port 2 Port 5 Pin Name P10 to P17 P20 to P27 P53 P54 P55 P56 P60 P61 P62 P63 Number of Pins 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 7 1 1 Direction I/O Output I/O I/O I/O I/O Output Output Output Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O R Direction Setting Unit Bit (Fixed) Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) Bit Bit WAIT INT0 CS0 CS1 CS2 CS3 Port 6 Port 7 P70 P71 P72 P73 P74 P75 P80 P81 P82 P83 P84 P85 P86 P87 P90 P93 P94 P95 P96 PA0 to PA7 PZ2 PZ3 TA0IN/INT1 TA1OUT TA3OUT/INT2 TA4IN/INT3 TA5OUT INT4 TXD0 RXD0 SCLK0/ CTS0 STS0 Port 8 TXD1 RXD1 SCLK1/ CTS1 STS1 Port 9 INT5 TB0IN0 TB0IN1 TB0OUT0 TB0OUT1 AN0 to AN7, ADTRG (PA3) HWR Port A Port Z 91C630-41 2003-07-22 TMP91C630 Table 3.6.2 (a) I/O Registers and Their Specifications Port Port 1 X: Don't care I/O Registers Name P10 to P17 Input port Output port D8 to D15 bus Specification Pn PnCR 0 1 1 None PnFC 0 0 1 0 1 0 0 0 1 None 0 0 0 1 1 0 0 0 1 None 1 1 0 0 1 Port 2 Port Z P20 to P27 PZ2 Output port A16 to A23 output Input port (without PU) Input port (with PU) Output port HWR output 0 1 0 0 1 1 PZ3 Input port (without PU) Input port (with PU) Output port 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 0 0 0 1 1 Port 5 P53 Input port (without PU) Input port (with PU) Output port BUSRQ Input (without PU) BUSRQ Input (with PU) P54 Input port (without PU) Input port (with PU) Output port BUSAK output P55 Input port/ WAIT input (without PU) Input port/ WAIT input (with PU) Output port 0 1 0 1 0 0 1 0 0 1 P56 Input port/INT0 input (without PU) Input port/INT0 input (with PU) Output port Port 6 P60 to P63 P60 P61 P62 P63 Output port CS0 output CS1 output CS2 output CS3 output None 1 1 1 Port 7 P70 to P75 P70 P71 P72 P73 P74 P75 Input port Output port TA0IN input INT1 input TA1OUT output TA3OUT output INT2 input TA4IN input INT3 input TA5OUT output INT4 input 0 1 0 0 1 1 0 0 0 1 0 0 0 None 1 1 1 1 None 1 1 1 91C630-42 2003-07-22 TMP91C630 Table 3.6.2 (b) I/O Registers and Their Specifications Port Port 8 P80 X: Don't care I/O Registers PnCR 0 0 1 1 Name Specification Input port (without PU) Input port (with PU) Output port TXD0 output (Note1) Pn 0 1 PnFC 0 0 0 1 None 0 0 0 1 0 0 0 1 0 0 0 1 None 0 0 0 1 0 0 0 1 0 0 1 P81 Input port/RXD0 input (without PU) Input port/RXD0 input (with PU) Output port 0 1 0 1 0 0 1 0 0 1 1 P82 Input port/SCLK0/ CTS0 input (without PU) Input port/SCLK0/ CTS0 input (with PU) Output port SCLK0 output P83 Input port (without PU) Input port (with PU) Output port STS0 output 0 1 0 0 1 1 P84 Input port (without PU) Input port (with PU) Output port TXD1 output (Note1) 0 1 0 0 1 1 P85 Input port/RXD1 input (without PU) Input port/RXD1 input (with PU) Output port 0 1 0 1 0 0 1 0 0 1 1 P86 Input port/SCLK1/ CTS1 input (without PU) Input port/SCLK1/ CTS1 input (with PU) Output port SCLK1 output P87 Input port (without PU) Input port (with PU) Output port STS1 output 0 1 0 0 1 1 0 1 0 0 1 0 0 1 1 None Port 9 P90 Input port Output port INT5 input P93 to P96 P93 P94 P95 P96 Port A PA0 to PA7 PA3 Input port Output port TB0IN0 input TB0IN1 input TB0OUT0 output TB0OUT1 output Input port AN0 to AN7 (Note 2) ADTRG input (Note 3) None 1 1 Note 1: If P80 and P84 are used as open-drain output port, they are need to set registers ODE 91C630-43 2003-07-22 TMP91C630 After a Reset the port pins listed below function as general-purpose I/O port pins. A Reset sets I/O pins which can be programmed for either input or output to be input port pins. Setting the port pins for internal function use must be done in software. Note about bus release and programmable pull-up I/O port pins When the bus is released (e.g. when BUSAK 0), the output buffers for D0 to D15, A0 to A23, and the control signals ( RD , WR , HWR and CS0 to CS3 ) are off and are set to High-impedance. However, the output of built-in programmable pull-up resistors are kept before the bus is released. These programmable pull-up resistors can be selected ON/OFF by programmable when they are used as the input ports. When they are used as output ports, they cannot be turned ON/OFF in software. Table 3.6.3 shows the pin states after the bus has been released. Table 3.6.3 Pin States (after Bus Release) Pin Names D0 to D7 P10 to P17 (D8 to D15) A0 to A15 P20 to P27 (A16 to A23) RD WR Pin State (after Bus Release) Used as Port Unchanged (e.g. not set to High-impedance (High-Z)) First all bits are set High, then they are set to High-Impedance (High-Z). Unchanged (e.g. not set to High-impedance (High-Z)) Used for Function High-Impedance (High-Z) PZ2 ( HWR ) The output buffer is set to OFF. The programmable pull-up resistor is set to ON irrespective of the output latch. P60 ( CS0 ) P61 ( CS1 ) P62 ( CS2 ) P63 ( CS3 ) 91C630-44 2003-07-22 TMP91C630 Figure 3.6.1 shows an example external interface circuit when the bus release function is used. When the bus is released, neither the internal memory nor the internal I/O can be accessed. However, the internal I/O continues to operate. As a result, the watchdog timer also continues to run. Therefore, the bus release time must be taken into account and care must be taken when setting the detection time for the WDT. RD WR PZ2 ( HWR ) System control bus P60 ( CS0 ) P61 ( CS1 ) P62 ( CS2 ) P63 ( CS3 ) P20 (A16) to P27 (A23) Address bus (A23 to A16) Figure 3.6.1 Interface Circuit Example (Using Bus Release Function) The above circuit is necessary to set the signal level when the bus is released. A reset sets ( RD ) and ( WR ), P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 ), P63 ( CS3 ) to output, and PZ2 ( HWR ) and P54 ( BUSAK ) to input with pull-up resistor. 91C630-45 2003-07-22 TMP91C630 3.6.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting, the control register P1CR to 0 and sets Port 1 to input mode. In addition to functioning as a general-purpose I/O port, Port 1 can also function as an address data bus (D8 to D15). In case of AM1 0, and AM0 1 (outside 16-bit data bus), port 1 always functions as the data bus (D8 to D15) irrespective of the setting in P1CR control register. Reset Direction control (on bit basis) P1CR write Output latch Internal data bus Output buffer P1 write Port 1 P10 to P17 (D8 to D15) P1 read Figure 3.6.2 Port 1 Port 1 Register 7 Bit symbol P1 (0001H) Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 Bit symbol P1CR (0004H) Read/Write After reset Function P17C 0 6 P16C 0 5 P15C 0 4 P14C W 0 0: In 3 P13C 0 1: Out 2 P12C 0 1 P11C 0 0 P10C 0 Note: Read-modify-write is prohibited for P1CR. Port 1 I/O setting 0 Input 1 Output Figure 3.6.3 Register for Port 1 91C630-46 2003-07-22 TMP91C630 3.6.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, Port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets Port 2 to address bus. Reset S Function control (on bits basis) Internal data bus P2FC write S latch B P2 write Selector Output A Output buffer Port 2 P20 to P27 (A16 to A23) P2 read Internal A16 to A23 Figure 3.6.4 Port 2 Port 2 Register 7 Bit symbol P2 (0006H) Read/Write After reset P27 6 P26 5 P25 4 P24 R/W 3 P23 2 P22 1 P21 0 P20 Output latch register is set to 1 Port 2 Function Register 7 P2FC (0009H) Read/Write After reset Function Note: Bit symbol P27F 1 6 P26F 1 5 P25F 1 0: Port 4 P24F W 1 3 P23F 1 2 P22F 1 1 P21F 1 0 P20F 1 1: Address bus (A23 to A16) Read-modify-write is prohibited for P2FC. Figure 3.6.5 Register for Port 2 91C630-47 2003-07-22 TMP91C630 3.6.3 Port 5 (P53 to P56) Port 5 is an 4-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and the function register P5FC to 0 and sets P52 to P56 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port, Port 5 also functions as I/O for the CPU's control/status signal. Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Output latch P5 write P-ch (Programmable pull-up) P53 ( BUSRQ ) P5 read Internal BUSRQ Figure 3.6.6 Port 53 91C630-48 2003-07-22 TMP91C630 Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Selector S Output latch P5 write BUSAK P-ch (Programmable pull-up) P54 ( BUSAK ) Output buffer A B P5 read Figure 3.6.7 Port 54 Reset Direction control (on bit basis) P5CR write Internal data bus S Output latch P5 write P-ch (Programmable pull-up) P55 ( WAIT ) Output buffer P5 read Internal WAIT Figure 3.6.8 Port 55 91C630-49 2003-07-22 TMP91C630 Reset Direction control (on bit basis) P5CR write Internal data bus Function control (on bit basis) P5FC write S Output latch P5 write Output buffer S P5 write B P-ch (Programmable pull-up) P56 (INT0) Selector A Level or edge & rising edge or falling edge IIMC0 INT0 Figure 3.6.9 Port 56 91C630-50 2003-07-22 TMP91C630 Port 5 Register 7 Bit symbol P5 (000DH) Read/Write After reset Function 6 P56 5 P55 R/W 4 P54 3 P53 2 1 0 Data from external port (Output latch register is set to 1) 0: Pull-up resistor OFF 1: Pull-up resistor ON Port 5 Control Register 7 Bit symbol P5CR (0010H) Read/Write After reset Function 6 P56C 0 5 P55C W 0 0: In 4 P54C 0 1: Out 3 P53C 0 2 1 0 I/O setting 0 Input 1 Output Port 5 Function Register 7 Bit symbol P5FC (0011H) Read/Write After reset Function 6 P56F W 0 0: Port 1: INT0 input 5 4 P54F W 0 0: Port 1: BUSAK 3 P53F 0 0: Port 1: BUSRQ 2 1 0 Note 1: Read-modify-write are prohibited for registers P5CR and P5FC. Note 2: When port 5 is used in the input mode, P5 register controls the built-in pull-up resistor. Read-modify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When P55 pin is used as a WAIT pin, clear P5CR Figure 3.6.10 Register for Port 5 91C630-51 2003-07-22 TMP91C630 3.6.4 Port 6 (P60 to P63) Port 6 is a 4-bit output port. When reset, the P62 output latch is cleared to 0 while the P60, P61 and P63 output latches are set to 1. In addition to functioning as an output port, this port can output standard chip select signals ( CS0 to CS3 ). These settings are made by using the P6FC register. When reset, the P6FC register has all of its bits cleared to 0, so that the port is set for output mode. Reset Internal data bus Funtion control (on bit basis) P6FC write S S Output lacth P6 write A B Selector Output buffer P60 ( CS0 ), P61 ( CS1 ), P63 ( CS3 ) P6 read CS0 , CS1 , CS3 Figure 3.6.11 Port 60, 61 and 63 Reset Function control Internal data bus (on bit basis) P6FC write S Selector R Output latch P6 write CS2 A B P62 ( CS2 ) Output buffer P6 read Figure 3.6.12 Port 62 91C630-52 2003-07-22 TMP91C630 Port 6 Register 7 P6 (0012H) Read/Write After reset Bit symbol 6 5 4 3 P63 2 P62 R/W 1 P61 0 P60 Output latch Output latch Output latch register is register is register is set to 1. set to 1. clear to 0. Port 6 Function Register 7 Bit symbol P6FC (0015H) Read/Write After reset Function Note: Read-modify-write is prohibited for the registers P6FC. 0 1 0 1 0 1 0 1 Port (P60) CS0 6 5 4 3 P63F 0 2 P62F W 0 0: Port 1 P61F 0 1: CS 0 P60F 0 Port (P61) CS1 Port (P62) CS2 Port (P63) CS3 Figure 3.6.13 Register for Port 6 91C630-53 2003-07-22 TMP91C630 3.6.5 Port 7 (P70 to P75) Port 7 is a 6-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port 7 to be an input port. In addition to functioning as a general-purpose I/O port, the individual port pins can also have the following functions: port pins 70 and 73 can function as the inputs TA0IN and TA4IN to the 8-bit timer, and port pins 71, 72 and 74 can function as the 8-bit timer outputs TA1OUT, TA3OUT and TA5OUT. For each of the output pins, timer output can be enabled by writing a 1 to the corresponding bit in the Port 7 function register (P7FC). Resetting clears all bits of the registers P7CR and P7FC to 0, and sets all bits to be input port pins. Reset Direction control (on bit basis) P7CR write Function control (on bit basis) Internal data bus P7FC write S Output latch SB P7 write Selector INT1 INT3 INT4 P70 (TA0IN/INT1) P73 (TA4IN/INT3) P75 (INT4) P7 read A Level or edge and rising edge or falling edge TA0IN TA4IN IIMC0 Figure 3.6.14 Ports 70, 73 and 75 91C630-54 2003-07-22 TMP91C630 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus S Output latch P7 write AS Selector Timer F/F out B B Selector P7 read SA P71 (TA1OUT) P74 (TA5OUT) TA1OUT: 8-bit TMRA1 TA5OUT: 8-bit TMRA5 Figure 3.6.15 Ports 71 and 74 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write Internal data bus Function control (on bit basis) P7FC write S Output latch Timer F/F out AS Selector B B Selector P72 (TA3OUT/INT2) P7 write (TA3OUT: 8-bit TMRA3) P7 read SA INT2 Edge or level & Rising edge or falling edge IIMC0 Figure 3.6.16 Port 72 91C630-55 2003-07-22 TMP91C630 Port 7 Register 7 P7 Bit symbol (0013H) Read/Write After reset 6 5 P75 4 P74 3 P73 R/W 2 P72 1 P71 0 P70 Data from external port (Output register is set to 1) Port 7 Control Register 7 P7CR Bit symbol (0016H) Read/Write After reset 6 5 P75C 0 4 P74C 0 3 P73C W 0 2 P72C 0 1 P71C 0 0 P70C 0 Port 7 I/O setting 0 Input 1 Output Port 7 Function Register 7 P7FC (0017H) Read/Write After reset Function Bit symbol 6 P72F2 W 0 0: Port 1: INT2 input 5 P75F W 0 0: Port 1: INT4 input 4 P74F 0 3 P73F W 0 2 P72F1 W 0 1 P71F 0 0 P70F W 0 0: Port 0: Port 1: TA5OUT 1: INT3 input 0: Port 0: Port 0: Port 1: TA3OUT 1: TA1OUT 1: INT1 input Note: Read-modify-write are prohibited for the registers P7CR and P7FC. Setting P71 as 8-bit timer output 1 P7FC Figure 3.6.17 Port 7 Registers 91C630-56 2003-07-22 TMP91C630 3.6.6 Port 8 (P80 to P87) Port pins 80 to 87 Port pins 80 to 87 constitute a 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets P80 to P87 to be an input port. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port pins, P80 to P87 can also function as the I/O for serial channel 0. These function can be enabled for I/O by writing a 1 to the corresponding bit of the Port 8 Function Register (P8FC). Resetting clears all bits of the registers P8CR and P8FC to 0 and sets all bits to be input port pins. (with pull-up resistors). (1) Port pins 80 (TXD0) and 84 (TXD1) As well as functioning as I/O port pins, port pins 80 and 84 can also function as serial channel TXD output pins. These port pins feature a programmable open-drain function. Reset Direction control (Each bit can be set individually.) P8CR write Internal data bus Function control (Each bit can be set individually.) P8FC write S Output latch P8 write TXD0 or TXD1 A S P80 (TXD0) P84 (TXD1) P-ch (Programmable pull-up) Selector B S B Open-drain possible ODE Selector P8 read A Figure 3.6.18 Port Pins 80 and 84 91C630-57 2003-07-22 TMP91C630 (2) Port pins 81 (RXD0) and 85 (RXD1) Port pins 81 and 85 are I/O port pins and can also be used as RXD input pin for the serial channels. Reset Direction control (Each bit can be set individually.) Internal data bus P8CR write S Output latch Output buffer P8 write P8 read RXD0 or RXD1 S B Selector A P81 (RXD0) P85 (RXD1) P-ch (Programmable pull-up) Figure 3.6.19 Port pins 81 and 85 (3) Port pins 82 ( CTS0 /SCLK0) and 86 ( CTS1 /SCLK1) Port pins 82 and 86 are I/O port pins and can also be used as the CTS input pins or SCLK I/O pins for the serial channels. Reset Direction control (Each bit can be set individually.) P-ch P8CR write Function control (Each bit can be set individually.) P8FC write S Output latch P8 write SCLK0 SCLK1 (Programmable pull-up) Internal data bus A S P82 (SCLK0/ CTS0 ) P86 (SCLK1/ CTS1 ) Selector B SB Selector P8 read SCLK0, CTS0 input SCLK1, CTS1 input A Figure 3.6.20 Ports 82 and 86 91C630-58 2003-07-22 TMP91C630 (4) Port pins 83 ( STS0 ) and 87 ( STS1 ) Port pins 83 and 87 are I/O port pins and can also be used as STS output pin for the received data request signal. Reset Direction control (on bit basis) P8CR write Function control (on bit basis) P8FC write S Output latch P8 write STS0 or STS1 Internal data bus S A Y Selector B S B Selector Y A P-ch (Programmable pull-up) P83 ( STS0 ) P87 ( STS1 ) P8 read Figure 3.6.21 Port Pins 83 and 87 91C630-59 2003-07-22 TMP91C630 Port 8 Register 7 Bit symbol P8 Read/Write (0018H) After reset Function P87 6 P86 5 P85 4 P84 R/W 3 P83 2 P82 1 P81 0 P80 Data from external port (Output latch register is set to 1) 0: Pull-up resistor OFF 1: Pull-up resistor ON Port 8 Control Register 7 Bit symbol P8CR (001AH) Read/Write After reset Function P87C 0 6 P86C 0 5 P85C 0 4 P84C W 0 0: In 1: Out 3 P83C 0 2 P82C 0 1 P81C 0 0 P80C 0 Port 8 I/O setting 0 Input 1 Output Port 8 Function Register 7 P8FC (001BH) Read/Write After reset Function Bit symbol P87F W 0 0: Port 1: STS1 output 6 P86F W 0 0: Port 1: SCLK1 output 5 4 P84F W 0 0: Port 1: TXD1 output 3 P83F W 0 0: Port 1: STS0 output 2 P82F W 0 0: Port 1: SCLK0 output 1 0 P80F W 0 0: Port 1: TXD0 input Note 1: Read-modify-write are prohibited for the registers P8CR and P8FC. Note 2: Writing 1 to bit 0 of the ODE register sets the TXD0, 1 pin to be open-drain. No register is provided for switching between the I/O port and RXD input functions of the P81/RXD0, P85/RXD1 pin. Hence, when Port 8 is used as an input port, the serial data input signals received on those pins are also input to the SIO. To set P80 and P84 for TXD0 and TXD1 outputs P8FC To set P82 and P86 for SCLK0 and SCLK1 outputs P8FC 1 1 To set P83 and P87 for STS0 and STS1 outputs P8FC Figure 3.6.22 Port 8 Register 91C630-60 2003-07-22 TMP91C630 3.6.7 Port 9 (P90, P93 to P96) Port 9 is an 5-bit general-purpose I/O port. Each bit can be set individually for input or output, Resetting sets port 9 to be an input port, It also sets all bits in the output latch register P9 to 1. In addtion to functioning as a general-purpose I/O port, the various pins of Port 9 can also function as the clock input for the 16-bit timer flipflop putput, on as input INT5. These functions cn be enabled by writing a 1 to the corresponding bits in the Port 9 function registers (P9FC). (1) P90 Reset Direction control (on bit basis) P9CR write Internal data bus S Output latch P90 (INT5) P9 write S B Selector Y A P9 read INT5 Level or edge and rising edge or falling edge IIMC1 P9FC Figure 3.6.23 Port 90 91C630-61 2003-07-22 TMP91C630 (2) P93 to P96 Reset Direction control (on bit basis) P9CR write S Output latch P9 write P9 read TB0IN0 TB0IN1 Internal data bus A Reset Direction control (on bit basis) P9CR write Function control (on bit basis) P9FC write S Output latch A P9 write Timer F/F OUT TB0OUT0: 16-bit TMRB0 TB0OUT1: 16-bit TMRB0 P93 (TB0IN0) P94 (TB0IN1) S B Selector S P95 (TB0OUT0) P96 (TB0OUT1) Selector B B Selector P9 read SA Figure 3.6.24 Port Pins P93 to P96 91C630-62 2003-07-22 TMP91C630 Port 9 Register 7 Bit symbol Read/Write P9 (0019H) After reset 6 P96 5 P95 R/W 4 P94 3 P93 2 1 0 P90 R/W Data from external port (Output latch register is set to 1) Data from external port (Output latch register is set to 1) Port 9 Control Register 7 P9CR (001CH) Read/Write After reset Function Bit symbol 6 P96C 0 5 P95C W 0 4 P94C 0 0: In 1: Out 3 P93C 0 2 1 0 P90C W 0 Port 9 I/O setting 0 Input 1 Output Port 9 Function Register 7 P9FC (001DH) Read/Write After reset Function Bit symbol 6 P96F W 0 5 P95F W 0 4 3 2 1 0 P90F W 0 0: Port 1: INT5 input 0: Port 0: Port 1: TB0OUT1 1: TB0OUT0 To set P95 for TB0OUT0 output 1 P9FC Figure 3.6.25 Port 9 Registers 91C630-63 2003-07-22 TMP91C630 3.6.8 Port A (PA0 to PA7) Port A is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. Internal data bus Port A read PA0 to PA7 ( ADTRG , AN0 to AN7) Conversion result register AD read AD converter Channel selector ADTRG (for PA3 only) Figure 3.6.26 Port A Port A Register 7 Bit symbol PA (001EH) Read/Write After reset Note: PA7 6 PA6 5 PA5 4 PA4 R 3 PA3 2 PA2 1 PA1 0 PA0 Data from external port The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.6.27 Port A Register 91C630-64 2003-07-22 TMP91C630 3.6.9 Port Z (PZ2, PZ3) Port Z is a 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting clears all bits of the output latch PZ to 1, the control register PZCR and the function register PZFC to 0 and sets PZ2 and PZ3 to input mode with pull-up register. In addition to functioning as a general-purpose I/O port. Port Z also functions as I/O for the CPU's control/status signal. Reset Direction control (on bit basis) PZCR write Function control Internal data bus (on bit basis) PZFC write S Selector S Output latch PZ write HWR P-ch (Programmable pull-up) PZ2 ( HWR ) Output buffer A B PZ read Figure 3.6.28 Port Z2 Reset Direction control (on bit basis) Internal data bus PZCR write S Output latch PZ write PZ read S Output buffer B P-ch (Purogrammable pull-up) PZ3 Selector A Figure 3.6.29 Port Z3 91C630-65 2003-07-22 TMP91C630 Port Z Register 7 Bit symbol PZ (007DH) Read/Write After reset Function 6 5 4 3 PZ3 R/W 2 PZ2 1 0 Data from external port (Note) 0: Pull-up resistor OFF 1: Pull-up resistor ON Note: Output latch register is set to 1. Port Z Control Register 7 PZCR (007EH) Read/Write After reset Function Bit symbol 6 5 4 3 PZ3 W 0 0: In 1: Out 2 PZ2 0 1 0 Setting Port Z as I/O 0 Input 1 Output Port Z Control Register 7 PZFC (007FH) Read/Write After reset Function Bit symbol 6 5 4 3 2 PZ2F W 0 0: Port 1: HWR 1 0 Figure 3.6.30 Port Z Registers 91C630-66 2003-07-22 TMP91C630 3.7 Chip Select/Wait Controller On the TMP91C630, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 plus any other). The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the Port 6 function register P6FC must be set. External connection of ROM and SRAM is supported. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin which controls these states is the bus wait request pin ( WAIT ). 3.7.1 Specifying an Address Area The address areas CS0 to CS3 are specified using the memory start address registers (MSAR0 to MSAR3) and the memory address mask registers (MAMR0 to MAMR3). During each bus cycle, a compare operation is performed to determine whether or not the address specified on the bus corresponds to a location in one of the areas CS0 to CS3. If the result of the comparison is a match, it indicates that the corresponding CS area is to be accessed. If so, the corresponding CS0 to CS3 pin outputs the chip select signal and the bus cycle proceeds according to the settings in the corresponding B0CS to B3CS chip select/wait control register. See 3.7.2, chip select/wait control registers. 91C630-67 2003-07-22 TMP91C630 (1) Memory start address registers Figure 3.7.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 determine the start addresses for the memory areas CS0 to CS3 respectively. The eight most significant bits (A23 to A16) of the start address should be set in MSAR0 (00C8H)/ MSAR1 (00CAH) MSAR2 (00CCH)/ MSAR3 (00CEH) Bit symbol Read/Write After reset Function 1 1 1 1 S23 6 S22 5 S21 4 S20 R/W 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.7.1 Memory Start Address Register Start address Address 000000H 64 Kbytes Value in start address register (MSAR0 to MSAR3) 000000H ..................... 00H 010000H ..................... 01H 020000H ..................... 02H 030000H ..................... 03H 040000H ..................... 04H 050000H ..................... 05H 060000H ..................... 06H to to FF0000H ..................... FFH FFFFFFH Figure 3.7.2 Relationship between Start Address and Start Address Register Value 91C630-68 2003-07-22 TMP91C630 (2) Memory address mask registers Figure 3.7.3 shows the memory address mask registers. The size of each of the areas CS0 to CS3 can be set by specifying a mask in the corresponding memory address mask register (MAMR0 to MAMR3). Each bit in a memory address mask register (MAMR0 to MAMR3) which is set to 1 masks the corresponding bit of the start address which has been set in the corresponding memory start address register (MSAR0 to MSAR3). The compare operation used to determine whether or not a bus address is in one of the areas CS0 to CS3 only compares address bits for which a 0 has been set in the corresponding bit position in the corresponding memory address mask register. Also, the address bits which each memory address mask register can mask vary from register to register; hence, the possible size settings for the areas CS0 to CS3 differ accordingly. Memory Address Mask Register (for CS0 Area) 7 MAMR0 (00C9H) Read/Write After reset Function Bit symbol V20 1 6 V19 1 5 V18 1 4 V17 R/W 1 3 V16 1 2 V15 1 1 V14 to 9 1 0 V8 1 Sets size of CS0 area 0: used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes. Memory Address Mask Register (CS1) 7 MAMR1 Bit symbol (00CBH) Read/Write After reset Function V21 1 6 V20 1 5 V19 1 4 V18 R/W 1 3 V17 1 2 V16 1 1 V15 to 9 1 0 V8 1 Sets size of CS0 area 0: used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2 and CS3) 7 MAMR2 (00CDH)/ Bit symbol MAMR3 (00CFH) Read/Write After reset Function V22 1 6 V21 1 5 V20 1 4 V19 R/W 1 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area 0: used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.7.3 Memory Address Mask Registers 91C630-69 2003-07-22 TMP91C630 (3) Setting memory start addresses and address areas Figure 3.7.4 shows an example in which CS0 is specified to be a 64-Kbyte address area starting at 010000H. First, MSAR0 Memory end address CS0 area size (64 Kbytes) Memory start address 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 H V20 V19 V18 V17 V16 V15 V14 to V9 V8 MAMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.7.4 Example Showing How to Set the CS0 Area A reset sets MSAR0 to MSAR3 and MAMR0 to MAMR3 to FFH. In addition, B0CS 91C630-70 2003-07-22 TMP91C630 (4) Address area size specification Table 3.7.1 shows the valid area sizes for each CS area and indicates which method can be used to make the size setting. A indicates that it is not possible to set the area size in question using the memory start address register and memory address mask register. If an area size for a CS area marked in the table is to be set, the start address must either be set to 000000H or to a value that is greater than 000000H by an integer multiple of the desired area size. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the lowest-numbered CS area has highest priority (e.g. CS0 has a higher priority than any other area). Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. 000000H 020000H 040000H 060000H b. Invalid start addresses 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. 000000H 010000H 030000H 050000H Table 3.7.1 Valid Area Sizes for Each CS Area Size (bytes) CS area 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M CS0 CS1 CS2 CS3 91C630-71 2003-07-22 TMP91C630 3.7.2 Chip Select/Wait Control Registers Figure 3.7.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 plus any other) are set in the respective chip select/wait control registers, B0CS to B3CS or BEXCS. Chip Select/Wait Control Register 7 B0CS (00C0H) Bit symbol Read/Write After reset B0E W 0 0: Disable 1: Enable 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: B1OM1 B1OM0 0 Data bus width 0: 16 bits 1: 8 bits B1BUS W 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: B2M 0 CS2 area selection 0: 16-Mbyte area 1: CS area B2OM1 B2OM0 W 1 0: Disable 1: Enable 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: B3OM1 B3OM0 0 Data bus width 0: 16 bits 1: 8 bits B3BUS W 0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: Don't care 11: 0 Data bus width 0: 16 bits 1: 8 bits BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 N) waits 011: 0 waits BEXW2 W 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 N) waits 011: 0 waits 0 0 0 0 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 N) waits 011: 0 waits B3W2 B3W1 0 0 0 Data bus width 0: 16 bits 1: 8 bits B2BUS 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 N) waits 011: 0 waits B2W2 B2W1 0 0 6 5 B0OM1 4 B0OM0 3 B0BUS W 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 010: (1 N) waits 011: 0 waits B1W2 1 B0W1 0 0 B0W0 0 Read-modify Function -write instructions are prohibited. 1xx: Reserved B1CS (00C1H) Bit symbol Read/Write B1E W 0 0: Disable 1: Enable B1W1 B1W0 Read-modify After reset -write Function instructions are prohibited. 1xx: Reserved B2CS (00C2H) Bit symbol Read/Write After reset B2E B2W0 Read-modify Functions -write instructions are prohibited. 1xx: Reserved B3CS (00C3H) Bit symbol Read/Write B3E W 0 0: Disable 1: Enable B3W0 Read-modify After reset Functions -write instructions are prohibited. 1xx: Reserved BEXCS (00C7H) Read-modify -write instructions are prohibited. Bit symbol Read/Write After reset Functions BEXW1 BEXW0 1xx: Reserved Master enable bit 0 1 CS area disable CS area enable Chip select output waveform selection 00 For ROM/SRAM 01 10 Don't care 11 Number of address area waits (See 3.7.2 (3) Wait Control.) Data bus width selection 0 1 16-bit data bus 8-bit data bus CS2 area selection 0 1 16-Mbyte area Specified address area Figure 3.7.5 Chip Select/Wait Control Registers 91C630-72 2003-07-22 TMP91C630 (1) Master enable bits Bit 7 ( 8 bits 2n 0 (Even number) 2n 1 (Odd number) 16 bits 2n 0 (Even number) 8 bits 16 bits 8 bits 16 bits 8 bits 16 bits 2n 1 (Odd number) 8 bits 16 bits 32 bits 2n 0 (Even number) 8 bits CPU Address 2n 2n 2n 2n 2n 2n 2n 2n 2n 2n 2n 2n 2n 2n 2n 0 0 1 1 0 1 0 1 2 1 2 0 1 2 3 0 2 1 2 3 4 1 2 4 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n 1 (Odd number) 8 bits 2n 2n 2n 2n 2n 2n 16 bits 2n 2n 2n Input data in bit positions marked xxxxx is ignored during a read. During a write, the bus lines corresponding to these bit positions go high-impedance and the write strobe signal for the bus remains inactive. 91C630-73 2003-07-22 TMP91C630 (3) Wait control Bits 0 to 2 ( Table 3.7.3 Wait Operation Settings 000 001 010 (1 No. of Waits 2 waits 1 wait N) waits Wait Operation Inserts a wait of two states, irrespective of the WAIT pin state. Inserts a wait of one state, irrespective of the WAIT pin state. Inserts one wait state, then continuously samples the state of the WAIT pin. While the WAIT pin remains Low, the wait continues; the bus cycle is prolonged until the pin goes High. Ends the bus cycle without a wait, regardless of the WAIT pin state. Do not set. 011 1xx 0 waits Reserved A Reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS 91C630-74 2003-07-22 TMP91C630 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: a. b. c. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 . The CS0 to CS3 pins can also function as pins P60 to P63. To output a chip select signal using one of these pins, set the corresponding bit in the Port 6 function register P6FC to 1. If a CS0 to CS3 address is specified which is actually an internal I/O, RAM or ROM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is clear to 0. MSAR0 MAMR0 B0CS 01H ........... Start address: 010000H 07H .......... Address area: 64 Kbytes 83H............... ROM/SRAM, 16-bit data bus, zero waits, CS0 area settings enabled 91C630-75 2003-07-22 TMP91C630 3.7.3 Connecting External Memory Figure 3.7.6 shows an example of how to connect external memory to the TMP91C630. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C630 CS0 CS1 CS2 Address bus CS CS CS CS A0 to A23 D8 to D15 D0 to D7 RD WR Upper byte ROM OE OE Lower byte ROM 8-bit RAM OE WE 8-bit I/O OE WE Figure 3.7.6 Example of External Memory Connection (ROM uses 16-bit bus; RAM and I/O use 8-bit bus.) A reset clears all bits of the Port 4 control register P6CR and the Port 6 function register P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. 91C630-76 2003-07-22 TMP91C630 3.8 8-Bit Timers (TMRA) The TMP91C630 features six built-in 8-bit timers. These timers are paired into three modules: TMRA01, TMRA23 and TMRA45. Each module consists of two channels and can operate in any of the following four operating modes. 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG with variable period) 8-bit pulse width modulation output mode (PWM period) variable duty cycle variable duty cycle with constant Figure 3.8.1 to 3.8.3 show block diagrams for TMRA01, TMRA23 and TMRA45. Each channel consists of an 8-bit up-counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by five control SFRs (special-function registers). Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. Table 3.8.1 Registers and Pins for Each Module Module Input pin for external clock Output pin for timer flip-flop Timer run register Timer register SFR (address) Timer mode register Timer flip-flop control register TMRA01 TA0IN (shared with P70) TA1OUT (shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 No TA3OUT (shared with P72) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TMRA45 TA4IN (shared with P73) TA5OUT (shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) External pin 91C630-77 2003-07-22 3.8.1 Prescaler 2 T1 T4 T16 T256 Timer flip-flop TA1FF Selector T1 T4 T16 8-bit up-counter (UC0) T1 T16 T256 TA01MOD Block Diagrams Prescaler clock: T0 Timer flip-flop output: TA1OUT External input clock: TA0IN Figure 3.8.1 TMRA01 Block Diagram 91C630-78 8-bit up-counter (CP0) Match detect TA0TRG TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer register TA1REG Internal bus TMRA1 interrupt output: INTTA1 TMP91C630 2003-07-22 Prescaler Prescaler clock: T0 2 T1 T4 T16 T256 Timer flip-flop TA3FF TA23RUN Figure 3.8.2 TMRA23 Block Diagram TA23MOD 91C630-79 Match 8-bit comparator detect (CP2) TA2TRG Match 8-bit comparator detect register (CP3) TA23MOD 8-bit timer register TA2REG 8-bit timer register TA3REG TA23RUN Register buffer 2 Internal bus TMRA2 interrupt output: INTTA2 TMRA2 match output: TA2TRG Internal bus TMRA3 interrupt output: INTTA3 TMP91C630 2003-07-22 Prescaler clock: T0 2 T1 T4 T16 T256 4 Prescaler Run/clear TA45RUN 8 16 32 64 128 256 512 Timer flip-flop TA5FF External input clock: TA4IN T1 T4 T16 8-bit up-counter (UC4) T1 T16 T256 TA45MOD Timer flip-flop output: TA5OUT Figure 3.8.3 TMRA45 Block Diagram TA45MOD 91C630-80 8-bit comparator (CP4) Match detect TA4TRG TA45MOD Match 8-bit comparator detect (CP5) 8-bit timer register TA5REG TMRA4 match output: TA4TRG Internal bus TMRA5 interrupt output: INTTA5 TMP91C630 2003-07-22 TMP91C630 3.8.2 Operation of Each Circuit (1) Prescalers The 9-bit prescaler in TMRA01 generates the clock source of TMRA01. The clock T0 is divided by 4 and input to this prescaler. T0 can be either fFPH or fc/16 and is selected using the prescaler clock selection register SYSCR0 at fc 36 MHz Prescaler Clock Selection Gear Value 000 (fc) 001 (fc/2) 3 Prescaler Output Clock Resolution T1 5 T4 7 T16 fc/2 (3.6 s) fc/28 (7.1 s) fc/2 (14 s) fc/2 (28 s) fc/2 (57 s) fc/211 (57 s) 11 10 9 T256 fc/2 (57 s) fc/212 (114 s) fc/213 (228 s) fc/214 (455 s) fc/215 (910 s) fc/215 (910 s) 11 fc/2 (0.22 s) fc/2 (0.9 s) fc/24 (0.4 s) fc/2 (0.9 s) fc/2 (1.8 s) fc/2 (3.6 s) fc/27 (3.6 s) 7 6 5 fc/26 (1.8 s) fc/2 (3.6 s) fc/2 (7.1 s) fc/2 (14 s) fc/29 (14 s) 9 8 7 (fFPH) 010 (fc/4) 011 (fc/8) 100 (fc/16) 10 (fc/16 clock) xxx: Don't care XXX (2) Up-counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4 or T16. The clock setting is specified by the value set in TA01MOD 91C630-81 2003-07-22 TMP91C630 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up-counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up-counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Up-counter Comparator (CP0) Timer registers 0 (TA0REG) Y Shift trigger Register buffers 0 Write Internal data bus Selector B A Write to TA0REG S Matching detection in PPG cycle 2n 1 overflow of PWM TA01RUN Figure 3.8.4 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When All these registers are write-only and cannot be read. 91C630-82 2003-07-22 TMP91C630 (4) Comparator (CP0 and CP1) The comparator compares the value in an up-counter with the value set in a timer register. If they match, the up-counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detect signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR 91C630-83 2003-07-22 TMP91C630 3.8.3 SFRs TMRA01 Run Register 7 TA01RUN Bit symbol (0100H) Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 6 5 4 3 I2TA01 2 TA01PRUN R/W 1 TA1RUN 0 0 TA0RUN 0 Timer Run/Stop control 0: Stop & clear 1: Run (Count up) TA0REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop & clear Run (Count up) I2TA01: Operation in IDLE2 mode TA01PRUN: Run prescaler TA1RUN: Run TMRA1 TA0RUN: Run TMRA0 Note: The values of bits 4 to 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN Bit symbol (0108H) Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 6 5 4 3 I2TA23 2 TA23PRUN R/W 1 TA3RUN 0 0 TA2RUN 0 Timer Run/Stop control 0: Stop & clear 1: Run (Count up) TA2REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop & clear Run (Count up) I2TA23: Operation in IDLE2 mode TA23PRUN: Run prescaler TA3RUN: Run TMRA3 TA2RUN: Run TMRA2 Note: The values of bits 4 to 6 of TA23RUN are undefined when read. Figure 3.8.5 TMRA Registers 91C630-84 2003-07-22 TMP91C630 TMRA45 Run Register 7 TA45RUN Bit symbol (0110H) Read/Write After reset Function TA4RDE R/W 0 Double buffer 0: Disable 1: Enable 0 IDLE2 0: Stop 1: Operate 0 6 5 4 3 I2TA45 2 TA45PRUN R/W 1 TA5RUN 0 0 TA4RUN 0 Timer Run/Stop control 0: Stop & clear 1: Run (Count up) TA4REG double buffer control 0 Disable 1 Enable Timer run/stop control 0 Stop & clear 1 Run (Count up) I2TA45: Operation during IDLE2 mode TA45PRUN: Run for prescaler TA5RUN: Run TMRA5 TA4RUN: Run TMRA4 Note: The values of bits 4 to 6 of TA45RUN are undefined when read. Figure 3.8.6 TMRA Registers 91C630-85 2003-07-22 TMP91C630 TMRA01 Mode Register 7 TA01MOD Bit symbol (0104H) Read/Write After reset Function TA01M1 0 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 01: 26 1 10: 27 1 11: 28 1 4 PWM00 R/W 0 3 TA1CLK1 0 2 TA1CLK0 0 1 TA0CLK1 0 0 TA0CLK0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode Source clock for TMRA1 00: TA0TRG 01: T1 10: T16 11: T256 Source clock for TMRA0 00: TA0IN pin 01: T1 10: T4 11: T16 TMRA0 source clock selection 00 01 10 11 TA0IN (external input) T1 (prescaler) T4 (prescaler) T16 (prescaler) TA01MOD TMRA1 source clock selection 00 01 10 11 PWM cycle selection 00 01 10 11 Reserved (26 (27 (28 1) 1) 1) clock source clock source clock source TMRA01 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0), 8-bit timer (TMRA1) Figure 3.8.7 TMRA Registers 91C630-86 2003-07-22 TMP91C630 TMRA23 Mode Register 7 TA23MOD Bit symbol (010CH) Read/Write After reset Function TA23M1 0 6 TA23M0 0 5 PWM21 0 PWM cycle 00: Reserved 01: 26 1 10: 27 1 11: 28 1 4 PWM20 R/W 0 3 TA3CLK1 0 2 TA3CLK0 0 1 TA2CLK1 0 0 TA2CLK0 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode TMRA3 clock for TMRA3 00: TA2TRG 01: T1 10: T16 11: T256 TMRA2 clock for TMRA2 00: Reserved 01: T1 10: T4 11: T16 TMRA2 source clock selection 00 01 10 11 Reserved T1 (prescaler) T4 (prescaler) T16 (prescaler) TA23MOD TMRA3 source clock selection 00 01 10 11 PWM cycle selection 00 01 10 11 Reserved (26 (27 (28 1) 1) 1) clock source clock source clock source TMRA23 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0), 8-bit timer (TMRA3) Figure 3.8.8 TMRA Registers 91C630-87 2003-07-22 TMP91C630 TMRA45 Mode Register 7 TA45MOD Bit symbol (0114H) Read/Write After reset Function TA45M1 0 6 TA45M0 0 5 PWM41 0 PWM cycle 00: reserved 01: 26 1 10: 27 1 11: 28 1 4 PWM40 R/W 0 3 TA5CLK1 2 TA5CLK0 1 TA4CLK1 0 TA4CLK0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 Source clock for TMRA5 00: TA4TRG 01: T1 10: T16 11: T256 0 0 Source clock for TMRA4 00: TA4IN pin 01: T1 10: T4 11: T16 Source clock for TMRA4 00 01 10 11 TA4IN (external input) T1 (prescaler) T4 (prescaler) T16 (prescaler) TA45MOD Soruce clock for TMRA5 00 01 10 11 PWM cycle 00 01 10 11 Reserved (26 (27 (28 1) 1) 1) clock source clock source clock source Operation mode for TMRA45 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA4), 8-bit timer (TMRA5) Figure 3.8.9 TMRA Registers 91C630-88 2003-07-22 TMP91C630 TMRA1 Flip-flop Control Register 7 TA1FFCR (0105H) Bit symbol Read/Write After reset Read-modify Function -write instruction is prohibited. 6 5 4 3 TAFF1C1 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care R/W 2 TAFF1C0 1 1 TAFF1IE R/W 0 TA1FF control for inversion 0: Disable 1: Enable 0 TAFF1IS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Inverse signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 Inversion of TA1FF 0 1 Disabled Enabled Control of TA1FF 00 01 10 11 Inverts the value of TA1FF Sets TA1FF to 1 Clears TA1FF to 0 Don't care Figure 3.8.10 TMRA Registers 91C630-89 2003-07-22 TMP91C630 TMRA3 Flip-flop Control Register 7 TA3FFCR (010DH) Bit symbol Read/Write After reset Read-modify Function -write instruction is prohibited. 6 5 4 3 TAFF3C1 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care R/W 2 TAFF3C0 1 1 TAFF3IE R/W 0 TA3FF control for inversion 0: Disable 1: Enable 0 TAFF3IS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA2 Inversion by TMRA3 Inversion of TA3FF 0 1 Disabled Enabled Control of TA3FF 00 01 10 11 Inverts the value of TA3FF Sets TA3FF to 1 Clears TA3FF to 0 Don't care Figure 3.8.11 TMRA Register 91C630-90 2003-07-22 TMP91C630 TMRA5 Flip-flop Control Register 7 TA5FFCR (0115H) Bit symbol Read/Write After reset Read-modify Function -write instruction is prohibited. 6 5 4 3 TAFF5C1 1 00: Invert TA5FF 01: Set TA5FF 10: Clear TA5FF 11: Don't care R/W 2 TAFF5C0 1 1 TAFF5IE R/W 0 TA5FF control for inversion 0: Disable 1: Enable 0 TAFF5IS 0 TA5FF inversion select 0: TMRA4 1: TMRA5 Inverse signal for timer flip-flop 5 (TA5FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA4 Inversion by TMRA5 Inversion of TA5FF 0 1 Disabled Enabled Control of TA5FF 00 01 10 11 Inverts the value of TA5FF Sets TA5FF to 1 Clears TA5FF to 0 Don't care Figure 3.8.12 TMRA Registers 91C630-91 2003-07-22 TMP91C630 3.8.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 8.8 s at fc as follows: * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH MSB TA01RUN TA01MOD TA1REG INTETA01 TA01RUN 7 - 0 0 X - 6 X 0 0 1 X 5 X X 1 0 X 4 X X 0 1 X 3 0 1 2 1 0 1 1 0 X 0 1 LSB 0 X 0 36 MHz, set each register Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.22 s at fc 36 MHz) as the input clock. Set TA1REG to 8.8 s T1 40 28H Enable INTTA1 and set it to Level 5. Start TMRA1 counting. X: Don't care, : No change Select the input clock using Table 3.8.4 Note : The input clocks for TMRA0 and TMRA1 differ as follows: TMRA0: Uses TA0IN input and can be selected from T1, T4 or T16 TMRA1: Match output of TMRA0 and can be selected from T1, T16, T256 91C630-92 2003-07-22 TMP91C630 b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.32 s square wave pulse from the TA1OUT pin at fc 36 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH 7 TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN 0 0 X X X 6 X 0 0 X X X X 5 X X 0 X 4 X X 0 X 3 0 0 1 2 1 0 0 1 0 X 1 1 1 1 1 0 X 1 1 Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.22 s at fc 36 MHz) as the input clock. Set the timer register to 1.32 s T1 2 3 Clear TA1FF to 0 and set it to invert on the match detect signal from TMRA1. Set P71 to function as the TA1OUT pin. Start TMRA1 counting. X X 1 X: Don't care, : No change T1 TA01RUN TA1OUT 0.67 s at fc 36 MHz Figure 3.8.13 Square Wave Output Timing Chart (50% duty) 91C630-93 2003-07-22 TMP91C630 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up-counter (when TA0REG 5) TMRA1 up-counter (when TA1REG 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.8.14 TMRA1 Count Up on Signal from TMRA0 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH 36 MHz, set the If T16 (3.6 s at 36 MHz) is used as the input clock for counting, set the following value in the registers: 0.225 s 3.6 s 62500 F424H; i.e. set TA1REG to F4H and TA0REG to 24H. 91C630-94 2003-07-22 TMP91C630 The comparator match signal is output from TMRA0 each time the up-counter UC0 matches TA0REG, where the up-counter UC0 is not be cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up-counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up-counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG 04H and TA0REG 80H Value of up-counter (UC1, UC0) TMRA0 comparator match detect signal 0000H 0080H 0180H 0280H 0380H 0480H Interrupt INTTA1 Timer output TA1OUT Inversion Figure 3.8.15 Timer Output by 16-Bit Timer Mode (3) 8-bit PPG (Programmable Pulse Generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-Low or active-High. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin (which can also be used as P71). tH tL t TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interruput INTTA1) TA1OUT TA0REG TA1REG Figure 3.8.16 8-Bit PPG Output Waveforms 91C630-95 2003-07-22 TMP91C630 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up-counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up-counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA1OUT Selector T1 T4 T16 TA01RUN Inversion TA01MOD Comparator Selector TA0REG-WR TA0REG Shift trigger Register buffer TA1REG TA01RUN Figure 3.8.17 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG and up-counter Match with TA1REG TA0REG (Value to be compared) Register buffer Q1 Q2 Shift from register buffer Q2 Q3 TA0REG (register buffer) write (Up-counter Q1) (Up-countner Q2) Figure 3.8.18 Operation of Register Buffer 91C630-96 2003-07-22 TMP91C630 Example: To generate 1/4-duty 113.636kHz pulses (at fc 36 MHz): 8.8 s * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH Calculate the value which should be set in the timer register. To obtain a frequency of 113.636 kHz, the pulse cycle t should be: t 1/113.636 kHz 8.8 s T1 0.22 s (at 36 MHz); 8.8 s 0.22 s 40 Therefore set TA1REG 40 28H. The duty is to be set to 1/4: t 1/4 8.8 s 2.2 s 0.22 s 10 Therefore, set TA0REG 10 0AH. 7 0 1 0 0 X X X 1 6 X 0 0 0 X X X X 5 X X 0 1 X 4 X X 0 0 X 3 X 1 1 0 2 0 X 0 0 1 1 0 0 1 0 1 1 1 1 0 0 1 0 0 X 1/4 2.2 s TA01RUN TA01MOD TA0REG TA1REG TA1FFCR P7CR P7FC TA01RUN X: Don't care, Stop TMRA0 and TMRA01 and clear it to 0. Set the 8-bit PPG mode, and select T1 as input clock. Write 0AH Write 28H Set TA1FF, enabling both inversion. 10 generates a negative logic pulse. Set P71 as the TA1OUT pin. X X 1 1 Start TMRA0 and TMRA1 counting. : No change 91C630-97 2003-07-22 TMP91C630 (4) 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (which is also used as P71). TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up-counter (UC0) matches the value set in the timer register TA0REG or when 2n 1 counter overflow occurs (n 6, 7 or 8 as specified by TA01MOD TA0REG and UC0 match 2n 1 overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) 1 counter overflow Figure 3.8.19 8-Bit PWM Waveforms Figure 3.8.20 shows a block diagram representing this mode. TA01RUN T1 T4 T16 TA1OUT TA1FFCR Selector 8-bit up counter (UC 0) Clear 2n 1 overflow control TAFF1 Invert TA01MOD TA01MOD Overflow Comparator INTTA0 TA0REG Selector TA0REG-WR TA01RUN Figure 3.8.20 Block Diagram of 8-Bit PWM Mode 91C630-98 2003-07-22 TMP91C630 In this mode the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. 1 Match with TA0REG Up-counter 2n 1 overflow Q1 Q2 Shift into TA0REG Q2 Q3 TA0REG (register buffer) write TA0REG (value to be compared) Register buffer Q1 Up-counter Q2 Figure 3.8.21 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at fc 36 MHz: 15.84 s 27.94 s * Clock state System clock: High frequency (fc) Clock gear: 1 (fc) Prescaler clock: fFPH To achieve a 27.94 s PWM cycle by setting T1 to 0.22 s (at fc 27.94 s 0.22 s 127 2n 1 127 Therefore n should be set to 7. Since the low-level period is 15.84 s when T1 0.22 s, set the following value for TA0REG: 15.84 s 0.22 s 72 48H MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN X: Don't care, 1 0 X X X 1 6 X 1 1 X X X X 5 X 1 0 X 4 X 0 0 X 3 X 1 1 2 X 0 0 LSB 0 0 01 1 0 1 1 1 1 0 X 36 MHz): Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (cycle: 27 the input clock. 1) and select T1 as Write 48H. Clear TA1FF to 0, enable the inversion. Set P71 and the TA1OUT pin. 1 Start TMRA0 counting. X X 1 : No change 91C630-99 2003-07-22 TMP91C630 Table 3.8.3 PWM Cycle at fc 36 MHz Select Prescaler Clock PWM Cycle Gear Value 000 (fc) 12.6 s 25.2 s 56.7 s 113 s 227 s 227 s 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 2 6 1 T4 T16 66.6 s 447 s 895 s 2 T1 25.4 s 50.8 s 114 s 229 s 7 1 T4 T16 457 s 901 s 2 T1 51 s 102 s 230 s 8 1 T4 T16 918 s 56.7 s 113 s 227 s 114 s 229 s 230 s 00 (fFPH) 459 s 1811 s 918 s 3621 s 457 s 1803 s 902 s 3607 s 447 s 1789 s 895 s 3585 s 895 s 3585 s 459 s 1811 s 7242 s 918 s 3621 s 14510 s 918 s 3621 s 14510 s 457 s 1803 s 7226 s 457 s 1803 s 7226 s 10 (fc/16 clcok) XXX XXX: Don't care (5) Settings for each mode Table 3.8.4 shows the SFR settings for each mode. Table 3.8.4 Timer Mode Setting Registers Register Name 8-bit timer 2 channels TA01MOD 00 TA1FFCR TAFF1IS Timer F/F Invert Signal Select 0: Lower timer output 1: Upper timer output Lower timer match, T1, T16, T256 (00, 01, 10, 11) Lower Timer Input Clock External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) External clock, T1, T4, T16 (00, 01, 10, 11) 16-bit timer mode 01 8-bit PPG 1 channel 10 8-bit PWM 1 channel 11 26 1, 27 1, 28 (01, 10, 11) 1 External clock, T1, T4, T16 (00, 01, 10, 11) T1, T16 , T256 (01, 10, 11) Output disabled 8-bit timer 1 channel 11 : Don't care 91C630-100 2003-07-22 TMP91C630 3.9 16-Bit Timer/Event Counters (TMRB) The TMP91C630 incorporates multifunctional 16-bit timer/event counter (TMRB0) which has the following operation modes: 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation (PPG) mode The timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, a timer flip-flop and a control circuit. The timer/event counter is controlled by an 11-byte control SFR. This chapter consists of the following items: Table 3.9.1 Differences Between TMRB0 Channel Spec External pins External clock/Capture trigger input pins Timer flip-flop output pins Timer run register Timer mode register Timer flip-flop control register TMRB0 TB0IN0 (also used as P93) TB0IN1 (also used as P94) TB0OUT0 (also used as P95) TB0OUT1 (also used as P96) TB0RUN (0180H) TB0MOD (0182H) TB0FFCR (0183H) TB0RG0L (0188H) TB0RG0H (0189H) TB0RG1L (018AH) TB0RG1H (018BH) TB0CP0L (018CH) TB0CP0H (018DH) TB0CP1L (018EH) TB0CP1H (018FH) SFR (address) Timer register Capture register 91C630-101 2003-07-22 3.9.1 INT output Internal data bus Register 0 Register 1 INTTB00 INTTB01 Internal data bus Block Diagrams Prescaler clock: T0 T1 Capture register 0 TB0CP0H/L TB0MOD 2 4 8 16 32 Run/ clear TB0RUN Timer flip-flop Timer flip-flop control TB0FF0 TB0FF1 Timer flip-flop output TB0OUT0 TB0OUT1 Over flow INT INTTBOF0 TA1OUT (from TMRA01) TB0IN0 TB0IN1 Capture, external INT input control Selector Count clock 16-bit up-counter (UC0) TB0MOD T1 TB0RUN Figure 3.9.1 Block Diagram of TMRB0 91C630-102 16-bit comparator (CP0) 16-bit timer register TB0RG0H/L TB0RUN Match detection 16-bit comparator (CP1) 16-bit time register TB0RG1H/L Internal data bus TMP91C630 2003-07-22 TMP91C630 3.9.2 Operation of Each Block (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock ( T0) is divided clock (divided by 4) from selected clock by the register SYSCR0 at fc 36 MHz Prescaler Clock Selection Clock Gear Value 000 (fc) 00 (fFPH) 001 (fc/2) 010 (fc/4) 011 (fc/8) 100 (fc/16) 10 (fc/16 clock) XXX Prescaler Clock Resolution T1 fc/23 (0.2 s) fc/24 (0.4 s) fc/2 (0.9 s) fc/2 (1.8 s) fc/2 (3.6 s) fc/27 (3.6 s) 7 6 5 T4 fc/25 (0.9 s) fc/26 (1.8 s) fc/2 (3.6 s) fc/2 (7.1 s) fc/2 (14 s) fc/29 (14 s) 9 8 7 T16 fc/27 (3.6 s) fc/28 (7.1 s) fc/29 (14 s) fc/210 (28 s) fc/211 (57 s) fc/211 (57 s) xxx: Don't care (2) Up-counter (UC0) UC0 is a 16-bit binary counter which counts up pulses input from the clock specified by TB0MOD 91C630-103 2003-07-22 TMP91C630 (3) Timer registers (TB0RG0H/L and TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up-counter UC0 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for timer register is executed using 2 byte data transfer instruction or using 1 byte date transfer instruction twice for lower 8 bits and upper 8 bits in order. The TB0RG0 timer register has a double-buffer structure, which is paired with register buffer. The value set in TB0RUN |